SRTS=Val_0x0
Shadow Request to Send Register
| SRTS | This is a shadow bit for the UART_MCR[RTS] bit, used to remove the burden of having to perform a read / modify write on the UART_MCR. This is used to directly control the UART_RTS. The UART_RTS is used to inform the modem or data set that the UART is ready to exchange data. When UART_MCR[AFCE] bit is set to 0, the UART_RTS is set low by programming UART_MCR[RTS] to a high. When UART_MCR[AFCE] bit is set to 1 and UART_FCR[FIFOE] set to 1, the UART_RTS signal is controlled in the same way, but is also gated with the Rx FIFO threshold trigger (UART_RTS signal is in active high when above the threshold) only when RTC flow-control trigger is disabled; otherwise it is gated by the Rx FIFO almost-full trigger, where almost full refers to two available slots in the FIFO (UART_RTS signal is in active high when above the threshold). Note: In Loopback mode (UART_MCR[LOOPBACK] bit set to 1), the UART_RTS signal is held in active high while the value of this bit is internally looped back to an input. 0 (Val_0x0): Shadow UART_RTS logic 1 1 (Val_0x1): Shadow UART_RTS logic 0 |